Simple update here, I’ve added the ability to read back the screen memory. The data bus for the FPGA has been bidirectional from the beginning, but it has so far only been used as an input. Whenever write enable is high and the computer is accessing the FPGA in some way, it will switch to being an output. To be able to read from screen ram, I had to change the way that it works. Previously, the ram was dual ported with one write port and one read port. The computer used the write port and the FPGA used the read port. Since the FPGA is constantly reading from whatever address it wants, there isn’t a way to use the existing read port to read from two different places at the same time. Luckily it’s pretty easy to change that ram to have two full ports, this way you can read from the same address you would write to. There is also a write port that the FPGA can access. It’s not used write now but it means I’ll be able to do things like clear the screen or draw on the screen directly from the FPGA. This should make things faster since the FPGA is clocked 300 times faster.

Reading from the screen memory is done in the exact same process as writing, but instead of writing, you read. The address registers are the same. In addition to being able to read the characters or pixels on the screen, there is also a ton of unused memory. In monochrome text mode for example, there are only 15*20=1200 bytes of memory used, while there are 38k bytes of total ram.

It is slower to access than the computers ram because you have to manually set the addresses each time, so instead of 4 cycles, you might need as many as 20 to load from an arbitrary address. If you are reading adjacent addresses it goes down to 10 though.

One idea that I’m still working on is a dedicated tile mode. I already made one in software, but having the FPGA do it itself would be much faster and simpler than doing it in code.

This is a pretty simple update but allows a lot of functionality.