Since my last update, I have made quite a bit of progress on this project. The biggest upgrade is with simulation. Most of the time spent working on this project is on the bus to and from work, which means I do not have access to hardware to test any new features. To solve this, I have created a simulation environment that lets me test the entire system somewhat accurately.

The way it works is I create a top level wrapper around the super6502 module that includes simulated sdram, sd card, uart, and most importantly a CPU. Testbenchs can then include this module and everything will start running. The syntax used to load the ROM in the FPGA with the correct image also works in simulation, and testing with new sd card images is easier as well, since I don’t need to mess around with a physical SD card. The downside is that it is much, much slower, but that is to be expected. Running a full chip simulation up to boot takes nearly 2 hours, where that same process is done in realtime in this gif:

boot.gif

Still, it is helpful and lets me get work done at all away from home. I also have all of these testbenches run whenever I push to gitlab. I also compile the bootloader and kernel, and generate the fpga image. This helps me if I make changes to one aspect and forget about others.

This has gotten me into a little bit of trouble when today, after a few months of not testing on hardware, the thing didn’t work at all. I traced it back to this issue #38, which worked in simulation but doesn’t actually work in hardware. The changes that I made to the sdram adapter don’t seem to work the same way.

Either way, simulation did help me implement many other features including the interrupt controller, memory mapper, and rtc.

Since one of the goals is to create a multitasking operating system, I followed what I was tought in ECE391. The earlier checkpoints are not as easy as they were in that class though since I have to write the hardware as well as the software. “Initialize the RTC” means that I have to actually make the RTC as well.

With the features that I have added, I am making good progress on getting a working kernel. The biggest things that I added, as mentioned before, are the interrupt controller, memory mapper, and rtc. The interrupt controller allows 128 different interrupts, with higher priority ones being served first. The memory mapper is a simple remapper which allows replacing the top 4 bits of the address with an additional 16 bits. This is how the cpu will be able to acess all of SDRAM despite its small address space. The RTC can act as both a counter as well as generate periodic interrupts, which you can see in the gif above as the repeated ‘A’s.

I plan to use the RTC interrupts to do preemptive multitasking. My next step is to add a ‘terminal’ driver. In 391 we use an emulated keyboard, but for this system we only have a serial interface. It can most likely be used in the same however.

After that, we need to support system calls and running programs.

I also added a README and some documentation, so check it out if you haven’t in a while: super6502 on gitlab