While I think it is fine to keep the boot rom in the FPGA, the main system memory does not belong in there. The DE10-Lite has 64MB of SDRAM on the board, which is what I will be adding.

Intel includes a basic SDRAM controller with Quartus and Platform Designer, but unlike some other IP, you can only use it in Platform Designer. Something else that is included in Platform Designer is an “External Bus to Avalon Bridge”, which allows an external peripheral to act as an Avalon master which is just what I want.

The SDRAM controller works as a generic memory interface, you read and write until it says its ready, and then you are good. Well, thats what I thought at least.

The main clock for the FPGA is 50MHz, and that is also what I am running the SDRAM at (through a 1ns delay PLL). The 6502 runs at 500KHz though, which is 100 times slower. As it turns out, the memory controller does not like holding the chip select low for that long.

What I ended up doing was setting up a simple state machine the latches the values at first, then waits until the next access before asserting them again.

Here is what the code looks like:

always_comb begin
    next_teststate = teststate;
    write = '0;
    _sdram_cs = '0;
    case (teststate)
    S_0: begin
        write = sdram_cs & ~cpu_rwb & cpu_phi2;
        _sdram_cs = sdram_cs & cpu_phi2;
        if (sdram_cs & ~cpu_rwb & ack)
            next_teststate = S_1;
    end
    S_1: begin
        if (~(sdram_cs & ~cpu_rwb))
            next_teststate = S_0;
    end
    endcase
end

the write signal comes from the chip select (which comes from the address) and the write signal as well as the clock signal. It is important to wait for the rising edge of the cpu clock is because the cpu asserts the address on the falling edge of the clock, but the write data is not asserted until the rising edge.

Stage S_0 is the default state where memory accesses are allowed. Once a memory access has occured and is completed, indicated by the ack signal, it transitions to state S_1, where memory accesses are not allowed until the cpu stops trying to access memory.

This works fine using SDRAM as data storage, but it could run into issues trying to execute code or using it as zero page, since sequential memory accesses are possible in those regions. For now though this will work as a start.